The present invention is related to polar decoding, more particularly, to a method for performing polar decoding with aid of notation transformation and associated polar decoder.
Recently, polar code has been chosen for utilization on 5G channels coding, however, it is essentially hard to reduce hardware complexity of polar decoders due to intrinsic latency of polar decoding. More specifically, hardware implementation of the polar decoders may require large circuit area and power consumption to achieve short decoding latency. On the other hand, additional power and hardware source may greatly increase along with high speed operations.
In a polar decoding procedure, some key operations may be repeated multiple times, which means sub-circuits for executing these operations may occupy a big portion of circuit area. In order to meet speed requirement of polar decoding, advanced wafer fabrication, high operating voltage, or extremely complicated circuit structure may be utilized for design of the aforementioned sub-circuits, however, some problems such as greatly increased power consumption, greatly increased circuit area, etc. may be introduced. Thus, a novel method and associated architecture are needed for solving the problems without introducing any side effect or in a way that introduces less side effect.